A focal plane array typically includes a two-dimensional array of detector elements, or pixels, organized by columns and rows. It is common for a circuit or imager within a pixel to accumulate charge from a photo-diode, the charge corresponding to the flux of light of various wavelengths incident on the photo-diode. Often, the charge is accumulated on a capacitive element which effectively integrates charge, producing a voltage that corresponds to the intensity of the flux over a given time interval called an integration interval.
In a traditional analog pixel, a well capacitor is coupled to a detector diode. The well capacitor integrates photo-current from the detector diode over an integration interval. Once per frame, the voltage on the well capacitor is transferred to a sample-and-hold capacitor and then transferred out, line by line, to an Analog to Digital Converter (ADC) which converts the voltage to a binary value. However, as pixel sizes have decreased, the ability of the well capacitor to store an effective amount of charge has diminished.
In-pixel ADC imaging offers improved photo-charge capacity even as the desired size of pixels continues to shrink (e.g., below 15 microns). A traditional in-pixel ADC design includes a quantizing analog front end circuit which accumulates charge over a relatively small capacitor and is reset (i.e., discharged) each time a threshold charge is stored on the capacitor. The pattern of charging and resetting is repeated as more photo-current integrates. Each reset event is “accumulated” (i.e., counted) with a digital counter circuit. Each frame, a global snapshot is taken by copying the digital counter contents to a snapshot register and then reading the snapshot registers out, line by line. The effect is to exponentially increase well capacity of the imager while maintaining a relatively small pixel size.